Device Design Consideration for 50 nm DRAM Using the Bulk FinFET

K. R. Han; B. G. Choi; T. Park; E. Yoon; J.-H. Lee

doi:https://doi.org/10.7567/SSDM.2004.B-4-1

2004 International Conference on Solid State Devices and Materials

2004年9月14日〜 2004年9月17日
Tower Hall Funabori, Tokyo, Japan

[B-4-1] Device Design Consideration for 50 nm DRAM Using the Bulk FinFET

K. R. Han、B. G. Choi、T. Park、E. Yoon、J.-H. Lee (1.School of Electrical Engineering and Computer Science, Kyungpook National University、2.School of Materials Science and Engineering, Seoul University)

https://doi.org/10.7567/SSDM.2004.B-4-1

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