[B-5-2] A Novel Dual-Metal Gate Integration Process for Sub-1nm EOT HfO2 CMOS Devices

J.F. Kang, C. Ren, H.Y. Yu, X.P. Wang, M-F. Li, D.S.H. Chan, Y-C. Yeo, Y.Y. Wang, D.-L. Kwong (1.Institute of Microelectronics, Peking University, 2.Silicon Nano Device Lab, Dept. of ECE, National University of Singapore, 3.Dept. of ECE, The University of Texas at Austin)

https://doi.org/10.7567/SSDM.2004.B-5-2