Optimization Technique of Number of Interconnect Layers and Circuit Area Based on Wire Length Distribution

Takanori Kyogoku; Junpei Inoue; Hidenari Nakashima; Kenichi Okada; Kazuya Masu

doi:https://doi.org/10.7567/SSDM.2004.P3-15

[P3-15] Optimization Technique of Number of Interconnect Layers and Circuit Area Based on Wire Length Distribution

Takanori Kyogoku, Junpei Inoue, Hidenari Nakashima, Kenichi Okada, Kazuya Masu (1.Precision and Intelligence Laboratory, Tokyo Institute of Technology)

https://doi.org/10.7567/SSDM.2004.P3-15

2004 International Conference on Solid State Devices and Materials

[P3-15] Optimization Technique of Number of Interconnect Layers and Circuit Area Based on Wire Length Distribution