[A-5-4] Reliable Extractions of EOT and Vfb in Poly-Si Gate High-k MISFETs through Advanced Modeling of Gate and Substrate Capacitances

N. Yasuda, H. Ota, T. Horikawa, T. Nabatame, H. Satake, A. Toriumi, Y. Tamura, T. Sasaki, F. Ootsuka (1.MIRAI-ASET, AIST, 2.MIRAI-ASRC, AIST, 3.University of Tokyo, 4.Selete, AIST)

https://doi.org/10.7567/SSDM.2005.A-5-4