The Japan Society of Applied Physics

[B-1-2] A 90nm Hybrid SOI CMOS Technology Integrating PDSOI and Bulk Devices for Bulk-designed MPU Performance Booster

S. Miyake, T. Suzuki, T. Watanabe, O. Fujita, N. Harada, K. Doumeki, T. Fukai, T. Syo, T. Moriya, S. Haruta, Y. Takeshita, M. Ikeda, K. Imai (1.Advanced Device Development Division, 2.Product Engineering Division, 3.Process Technology Division and, 4.Custom LSI Division NEC Electronics Corporation)

https://doi.org/10.7567/SSDM.2005.B-1-2