[J-5-4] Mechanism of Threshold Voltage Reduction and Hole Mobility Enhancement in pMOSFETs Employing Sub-1nm EOT HfSiON by Use of Substrate Fluorine Ion Implantation

Seiji Inumiya、Akira Uedono、Seiichi Miyazaki、Shingo Ohtsuka、Takeo Matsuki、Tetsunori Wada、Takayuki Aoyama、Keisaku Yamada、Yasuo Nara (1.Semiconductor Leading Edge Technologies, Inc. (Selete)、2.Univ. of Tsukuba、3.Hiroshima Univ.、4.Waseda Univ.)

https://doi.org/10.7567/SSDM.2006.J-5-4