[J-8-3] Effects of Optimization of Gate Edge Profile on sub-45nm Metal Gate High-k Dielectric Metal-Oxide-Semiconductor Field Effect Transistors Characteristics

C. Y. Kang、R. Choi、S. H. Bae、S. C. Song、M. M. Hussain、C. Young、D. Heh、G. Bersuker、B. H. Lee (1.SEMATECH、2.Microelectronics Research Center, Department of Electrical and Computer Engineering, The University of Texas)

https://doi.org/10.7567/SSDM.2006.J-8-3