The Japan Society of Applied Physics

[J-8-5] Full-Metal-Gate Integration of Dual-Metal-Gate HfSiON CMOS Transistors by Using Oxidation-Free Dummy-Mask Process

F. Ootsuka、Y. Tamura、Y. Akasaka、S. Inumiya、H. Nakata、M. Ohtsuka、T. Watanabe、M kitajima、Y. Nara、K. Nakamura (1.Semiconductor Leading Edge Technologies, Inc. (Selete))

https://doi.org/10.7567/SSDM.2006.J-8-5