Strain Efficiency Enhancement with Stress Intermedium Engineering (SIE) for Sub-65nm CMOS Scaling

Hung-Ming Chen; Chien-Chao Huang; Jiunn-Ren Hwang; Chang-Yun Chang; Yi-Ming Sheu; Ming-Yi Yang; Cheng-Kuo Wen; Shih-Chang Chen; Han-Jan Tao; Fu-Liang Yang

doi:https://doi.org/10.7567/SSDM.2006.P-3-22

[P-3-22] Strain Efficiency Enhancement with Stress Intermedium Engineering (SIE) for Sub-65nm CMOS Scaling

Hung-Ming Chen、Chien-Chao Huang、Jiunn-Ren Hwang、Chang-Yun Chang、Yi-Ming Sheu、Ming-Yi Yang、Cheng-Kuo Wen、Shih-Chang Chen、Han-Jan Tao、Fu-Liang Yang (1.Taiwan Semiconductor Manufacturing Company)

https://doi.org/10.7567/SSDM.2006.P-3-22

2006 International Conference on Solid State Devices and Materials

[P-3-22] Strain Efficiency Enhancement with Stress Intermedium Engineering (SIE) for Sub-65nm CMOS Scaling