Gate First PFET Poly-Si/TiN/Al2O3 Gate Stacks with Inversion Thicknesses Less than 15A for High Performance or Low Power CMOS Applications

B. P. Linder; V. Narayanan; V. K. Paruchuri; E. Cartier; S. Kanakasabapathy

doi:https://doi.org/10.7567/SSDM.2007.A-1-5

2007 International Conference on Solid State Devices and Materials

Sep 18, 2007 - Sep 21, 2007
Tsukuba International Congress Center (EPOCHAL TSUKUBA), Ibaraki, Japan

[A-1-5] Gate First PFET Poly-Si/TiN/Al2O3 Gate Stacks with Inversion Thicknesses Less than 15A for High Performance or Low Power CMOS Applications

B. P. Linder, V. Narayanan, V. K. Paruchuri, E. Cartier, S. Kanakasabapathy (1.IBM Semiconductor Research and Development Center, Research Division, 2.T. J. Watson Research Center, Yorktown Heights)

https://doi.org/10.7567/SSDM.2007.A-1-5

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