[A-3-2] Comprehensive Understanding of PBTI and NBTI reliability of High-k / Metal Gate Stacks with EOT Scaling to sub-1nm

Motoyuki Sato、Kikuo Yamabe、Kenji Shiraishi、Seiichi Miyazaki、Keisaku Yamada、Chihiro Tamura、Ryu Hasunuma、Seiji Inumiya、Takayuki Aoyama、Yasuo Nara、Yuzuru Ohji (1.Semiconductor Leading Edge Technologies, Inc. (Selete)、2.Univ. of Tsukuba、3.Hiroshima Univ.、4.Waseda Univ.)

https://doi.org/10.7567/SSDM.2007.A-3-2