A Breakthrough Electronic Lithography Process Through Si Layer for Self Aligning Gates in Planar Double-Gate Transistors for 32nm Node And Below

R. Wacquez; P. Coronel; MP. Samson; D. Delille; LR. Clement; V. Delaye; L. Baud; N. Loubet; J. Bustos; A. Pouydebasque; B. Guillaumot; T. Ernst; P. Masson; JP. Gouy; T. Skotnicki

doi:https://doi.org/10.7567/SSDM.2007.F-10-2

[F-10-2] A Breakthrough Electronic Lithography Process Through Si Layer for Self Aligning Gates in Planar Double-Gate Transistors for 32nm Node And Below

R. Wacquez, P. Coronel, MP. Samson, D. Delille, LR. Clement, V. Delaye, L. Baud, N. Loubet, J. Bustos, A. Pouydebasque, B. Guillaumot, T. Ernst, P. Masson, JP. Gouy, T. Skotnicki (1.ST Microelectronics, 2.NXP 850 rue J.Monnet, 3.CEA/Leti Minatec, 4.L2MP)

https://doi.org/10.7567/SSDM.2007.F-10-2

2007 International Conference on Solid State Devices and Materials

[F-10-2] A Breakthrough Electronic Lithography Process Through Si Layer for Self Aligning Gates in Planar Double-Gate Transistors for 32nm Node And Below