Delay-Compensation Flip-Flops for Timing-Error Tolerant Circuit Design

Kenichiro Hirose; Yasuo Manzawa; Masahiro Goshima; Shuichi Sakai

doi:https://doi.org/10.7567/SSDM.2007.P-5-1

2007 International Conference on Solid State Devices and Materials

2007年9月18日〜 2007年9月21日
Tsukuba International Congress Center (EPOCHAL TSUKUBA), Ibaraki, Japan

[P-5-1] Delay-Compensation Flip-Flops for Timing-Error Tolerant Circuit Design

Kenichiro Hirose、Yasuo Manzawa、Masahiro Goshima、Shuichi Sakai (1.Graduate School of Information Science and Technology, The University of Tokyo、2.Graduate School of Frontier Sciences, The University of Tokyo)

https://doi.org/10.7567/SSDM.2007.P-5-1

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