Additive Process Induced Strain (APIS) Technology for L<sub>g</sub> = 30nm Band-Edge High-k/Metal Gate nMOSFET

M. M. Hussain; K. Rader; C. Smith; C. Young; S. Suthram; C. Park; M. Cruz; P. D. Kirsch; R. Jammy

doi:https://doi.org/10.7567/SSDM.2008.A-7-2

2008 International Conference on Solid State Devices and Materials

Sep 23, 2008 - Sep 26, 2008
Tsukuba International Congress Center (EPOCHAL TSUKUBA), Ibaraki, Japan

[A-7-2] Additive Process Induced Strain (APIS) Technology for L_g = 30nm Band-Edge High-k/Metal Gate nMOSFET

M. M. Hussain¹, K. Rader², C. Smith³, C. Young¹, S. Suthram⁴, C. Park¹, M. Cruz¹, P. D. Kirsch¹, R. Jammy⁵ (1.SEMATECH, 2.Texas State Univ., 3.Univ. of North Texas, 4.Univ. of Florida, 5.IBM Assignee, USA)

https://doi.org/10.7567/SSDM.2008.A-7-2

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2008 International Conference on Solid State Devices and Materials

[A-7-2] Additive Process Induced Strain (APIS) Technology for Lg = 30nm Band-Edge High-k/Metal Gate nMOSFET

[A-7-2] Additive Process Induced Strain (APIS) Technology for L_g = 30nm Band-Edge High-k/Metal Gate nMOSFET