Low <i>V<sub>t</sub></i> Metal-Gate/High-k CMOS from Understanding the Mechanism to Innovative Solution (Invited)

A. Chin; C. H. Cheng; N. C. Su; S. J. Wang; C. C. Liao; C. P. Chou; H. L. Hwang

doi:https://doi.org/10.7567/SSDM.2008.A-8-1

2008 International Conference on Solid State Devices and Materials

2008年9月23日〜 2008年9月26日
Tsukuba International Congress Center (EPOCHAL TSUKUBA), Ibaraki, Japan

[A-8-1] Low V_t Metal-Gate/High-k CMOS from Understanding the Mechanism to Innovative Solution (Invited)

A. Chin^1,2、C. H. Cheng²、N. C. Su³、S. J. Wang³、C. C. Liao^1,2、C. P. Chou²、H. L. Hwang^1,4 (1.Nano-Electronics Consortium of Taiwan、2.National Chiao Tung Univ.、3.National Cheng Kung Univ.、4.National Tsing Hua Univ., Taiwan)

https://doi.org/10.7567/SSDM.2008.A-8-1

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2008 International Conference on Solid State Devices and Materials

[A-8-1] Low Vt Metal-Gate/High-k CMOS from Understanding the Mechanism to Innovative Solution (Invited)

[A-8-1] Low V_t Metal-Gate/High-k CMOS from Understanding the Mechanism to Innovative Solution (Invited)