[B-2-4] Advantages of Densely Packed Multi-Wire Transistors with a Planar Gate Structure and a Low-k Buried Insulator over Planar SOI Devices

M. Ono¹, K. Uchida², T. Tezuka¹ (1.Toshiba Corp., 2.Tokyo Tech., Japan)

https://doi.org/10.7567/SSDM.2008.B-2-4