[B-5-3] Stress Memorization Technique (SMT) for pMOS by Dopant Confinement Layer (DCL)

H. Ohta¹、K. Ikeda¹、H. Fukutome¹、M. Tajima²、K. Okabe²、K. Ohkoshi²、S. Satoh¹ (1.Fujitsu Labs. Ltd.、2.Fujitsu Microelectronics Ltd., Japan)

https://doi.org/10.7567/SSDM.2008.B-5-3