The Japan Society of Applied Physics

[B-7-2] Process Architecture for Spatial and Temporal Variability Improvement of SRAM Circuits at the 45nm Node

N. Planes1, V. Huard1, C. Laviron2, O. Callen1, J. Bonnouvrier1, O. Menut1, S. Haendler1, M. Haond1, F. Boeuf1 (1.STMicroelectronics, 2.CEA-LETI, France)

https://doi.org/10.7567/SSDM.2008.B-7-2