[B-7-2] Process Architecture for Spatial and Temporal Variability Improvement of SRAM Circuits at the 45nm Node

N. Planes¹、V. Huard¹、C. Laviron²、O. Callen¹、J. Bonnouvrier¹、O. Menut¹、S. Haendler¹、M. Haond¹、F. Boeuf¹ (1.STMicroelectronics、2.CEA-LETI, France)

https://doi.org/10.7567/SSDM.2008.B-7-2