Process Architecture for Spatial and Temporal Variability Improvement of SRAM Circuits at the 45nm Node

N. Planes; V. Huard; C. Laviron; O. Callen; J. Bonnouvrier; O. Menut; S. Haendler; M. Haond; F. Boeuf

doi:https://doi.org/10.7567/SSDM.2008.B-7-2

2008 International Conference on Solid State Devices and Materials

Sep 23, 2008 - Sep 26, 2008
Tsukuba International Congress Center (EPOCHAL TSUKUBA), Ibaraki, Japan

[B-7-2] Process Architecture for Spatial and Temporal Variability Improvement of SRAM Circuits at the 45nm Node

N. Planes¹, V. Huard¹, C. Laviron², O. Callen¹, J. Bonnouvrier¹, O. Menut¹, S. Haendler¹, M. Haond¹, F. Boeuf¹ (1.STMicroelectronics, 2.CEA-LETI, France)

https://doi.org/10.7567/SSDM.2008.B-7-2

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