[D-2-2] Scaling Trend of Analog Integrated Circuit with Process Variations on Future Ultra Deep Submicron CMOS Technology

T. Oshita¹、K. Tsutsui¹、N. Ishihara¹、K. Masu¹ (1.Tokyo Tech., Japan)

https://doi.org/10.7567/SSDM.2008.D-2-2