[P-5-2] Low-Power Image-Segmentation VLSI Design based on a Pixel-Block Scanning Architecture

K. Okazaki¹, K. Awane¹, N. Nagaoka¹, T. Sugahara¹, T. Koide¹, H. J. Mattausch¹ (1.Hiroshima Univ., Japan)

https://doi.org/10.7567/SSDM.2008.P-5-2