The Japan Society of Applied Physics

[P-5-6] Additional 12% Power Reduction in Practical Digital Chips of Low-Power Design using Post-Fabrication Clock-Timing Adjustment

E. Takahashi1、T. Susa2、M. Murakawa1、T. Furuya2、T. Higuchi1、S. Furuichi3、Y. Ueda3、A. Wada3 (1.AIST、2.Toho Univ.、3.Sanyo Electric Co., Ltd., Japan)

https://doi.org/10.7567/SSDM.2008.P-5-6