[P-5-6] Additional 12% Power Reduction in Practical Digital Chips of Low-Power Design using Post-Fabrication Clock-Timing Adjustment

E. Takahashi¹、T. Susa²、M. Murakawa¹、T. Furuya²、T. Higuchi¹、S. Furuichi³、Y. Ueda³、A. Wada³ (1.AIST、2.Toho Univ.、3.Sanyo Electric Co., Ltd., Japan)

https://doi.org/10.7567/SSDM.2008.P-5-6