Additional 12% Power Reduction in Practical Digital Chips of Low-Power Design using Post-Fabrication Clock-Timing Adjustment

E. Takahashi; T. Susa; M. Murakawa; T. Furuya; T. Higuchi; S. Furuichi; Y. Ueda; A. Wada

doi:https://doi.org/10.7567/SSDM.2008.P-5-6

2008 International Conference on Solid State Devices and Materials

Sep 23, 2008 - Sep 26, 2008
Tsukuba International Congress Center (EPOCHAL TSUKUBA), Ibaraki, Japan

[P-5-6] Additional 12% Power Reduction in Practical Digital Chips of Low-Power Design using Post-Fabrication Clock-Timing Adjustment

E. Takahashi¹, T. Susa², M. Murakawa¹, T. Furuya², T. Higuchi¹, S. Furuichi³, Y. Ueda³, A. Wada³ (1.AIST, 2.Toho Univ., 3.Sanyo Electric Co., Ltd., Japan)

https://doi.org/10.7567/SSDM.2008.P-5-6

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