[K-6-6] Fine-Grain Power-Gating Scheme of a CMOS/MTJ-Hybrid Bit-Serial Ternary Content-Addressable Memory

S. Matsunaga¹、A. Matsumoto¹、M. Natsui¹、T. Endoh¹、H. Ohno¹、T. Hanyu¹ (1.Tohoku Univ.)

https://doi.org/10.7567/SSDM.2009.K-6-6