The Japan Society of Applied Physics

[P-2-6] Low-Temperature Silicon Oxide Offset Spacer using Plasma Enhanced Atomic Layer Deposition for High-k/Metal Gate Transistor

T. Murata1, Y. Miyagawa1, Y. Nishida1, Y. Yamamoto1, T. Yamashita1, M. Matsuura1, K. Asai1 (1.Renesas Tech. Corp.)

https://doi.org/10.7567/SSDM.2009.P-2-6