Impact of Transistor Layout Configuration on Current Drive Performance in (100)/&lt;110&gt; and (100)/&lt;100&gt; SiGe channel pMOSFETs: Comparative Study to Si channel

K. Nakatsuka; H. Okamoto; H. Itokawa; K. Okano; T. Izumida; M. Kondo; T. Morooka; I. Mizushima; A. Azuma; N. Aoki; S. Inaba; Y. Toyoshima

doi:https://doi.org/10.7567/SSDM.2010.C-2-2

[C-2-2] Impact of Transistor Layout Configuration on Current Drive Performance in (100)/<110> and (100)/<100> SiGe channel pMOSFETs: Comparative Study to Si channel

K. Nakatsuka¹、H. Okamoto¹、H. Itokawa¹、K. Okano¹、T. Izumida¹、M. Kondo¹、T. Morooka¹、I. Mizushima¹、A. Azuma¹、N. Aoki¹、S. Inaba¹、Y. Toyoshima¹ (1.Toshiba Corp. , Japan)

https://doi.org/10.7567/SSDM.2010.C-2-2

2010 International Conference on Solid State Devices and Materials

[C-2-2] Impact of Transistor Layout Configuration on Current Drive Performance in (100)/<110> and (100)/<100> SiGe channel pMOSFETs: Comparative Study to Si channel