Gate Leakage Current Reduction in Two-Step Processed High-k Dielectrics for Low Power Applications

G. Bersuker; D. Heh; J. Huang; C. S. Park; A. Padovani; L. Larcher; P. D. Kirsch; R. Jammy

doi:https://doi.org/10.7567/SSDM.2010.C-8-5

[C-8-5] Gate Leakage Current Reduction in Two-Step Processed High-k Dielectrics for Low Power Applications

G. Bersuker¹, D. Heh¹, J. Huang¹, C. S. Park¹, A. Padovani², L. Larcher², P. D. Kirsch¹, R. Jammy¹ (1.SEMATECH , USA, 2.Università di Modena e Reggio Emilia , Italy)

https://doi.org/10.7567/SSDM.2010.C-8-5

2010 International Conference on Solid State Devices and Materials

[C-8-5] Gate Leakage Current Reduction in Two-Step Processed High-k Dielectrics for Low Power Applications