[P-5-11] A Sub-nanoampere Two-stage Power Management Circuit in 0.35-µm CMOS for Dust-Size Batteryless Sensor Nodes

M. Ugajin¹, T. Simamura¹, S. Mutoh¹, M. Harada¹ (1.NTT Corp. , Japan)

https://doi.org/10.7567/SSDM.2010.P-5-11