[P-5-14] An Experimental Verification of the Design Margin Analysis Method for Even-Stage Ring Oscillators with CMOS Latch

Y. Hirakawa¹、N. Mimura¹、A. Motomura¹、K. Nakamura¹ (1.Kyushu Inst. of Tech. , Japan)

https://doi.org/10.7567/SSDM.2011.P-5-14