[P-5-3] Write Speed Evaluation of Reconfigurable Spin Logic Block with SPRAM for 3D-Stacked Reconfigurable Spin Processor

R. Nakazawa¹、H. Kino¹、K. Kiyoyama^1,2、M. Koyanagi¹、T. Tanaka¹ (1.Tohoku Univ.、2.Nagasaki Inst. of Applied Science , Japan)

https://doi.org/10.7567/SSDM.2011.P-5-3