[J-5-1] 102.4 GS/s Impulse Sampling Circuit with Low Power and Low Timing Error Clock Generation

A. Toya^1,2, K. Sogo¹, N. Sasaki^1,3, T. Kikkawa¹ (1.Hiroshima Univ., 2.Kure National College of Tech., 3.Gunma National College of Tech. , Japan)

https://doi.org/10.7567/SSDM.2012.J-5-1