[J-6-3] -119.1 dBc/Hz Phase Noise Ring-VCO-Based PLL CMOS Circuit Using A Tunable Narrow-Deadzone Creator in Frequency Locked Loop

K. Sogo¹、A. Toya^1,2、T. Kikkawa¹ (1.Hiroshima Univ.、2.Kure National Collage of Tech. , Japan)

https://doi.org/10.7567/SSDM.2012.J-6-3