[PS-2-6] Analysis of Local Bending Stress Effect on CMOS Performance Fabricated in Thinned Si Chip for Chip-to-Wafer 3D Integration
H. Kino1, J. C. Bea1, M. Murugesan1, K. W. Lee1, T. Fukushima1, T. Tanaka1, M. Koyanagi1
(1.Tohoku Univ. , Japan)
https://doi.org/10.7567/SSDM.2012.PS-2-6