[PS-2-6] Analysis of Local Bending Stress Effect on CMOS Performance Fabricated in Thinned Si Chip for Chip-to-Wafer 3D Integration

H. Kino¹、J. C. Bea¹、M. Murugesan¹、K. W. Lee¹、T. Fukushima¹、T. Tanaka¹、M. Koyanagi¹ (1.Tohoku Univ. , Japan)

https://doi.org/10.7567/SSDM.2012.PS-2-6