[B-1-2] Thermal and Plasma Treatments for Improved (Sub-)1nm EOT Planar and FinFET-based RMG High-k Last Devices and Enabling a Simplified Scalable CMOS Integration Scheme

A. Veloso¹、G. Boccardi¹、L.A. Ragnarsson¹、Y. Higuchi²、H. Arimura^1,3、J.W. Lee^1,3、E. Simoen¹、M.J. Cho¹、Ph.J. Roussel¹、V. Paraschiv¹、X. Shi¹、T. Schram¹、S.A. Chew¹、S. Brus¹、A. Dangol¹、E. Vecchio¹、F. Sebaai¹、K. Kellens¹、N. Heylen¹、K. Devriendt¹、H. Dekkers¹、A. Van Ammel¹、T. Witters¹、T. Conard¹、I. Vaesen¹、O. Richard¹、H. Bender¹、R. Athimulam¹、A. Thean¹、N. Horiguchi¹ (1.Imec、2.Panasonic、3.K. U. Leuven (Belgium))

https://doi.org/10.7567/SSDM.2013.B-1-2