[D-6-2] Speed Enhancement at Vdd = 0.4 V and Randam τpd Variability Reduction of Silicon on Thin Buried Oxide (SOTB)
H. Makiyama1, Y. Yamamoto1, H. Shinohara1, T. Iwamatsu1, H. Oda1, N. Sugii1, K. Ishibashi2, Y. Yamaguchi1
(1.Low-power Electronics Association & Project (LEAP), 2.The Univ. of Electro-Communications (Japan))
https://doi.org/10.7567/SSDM.2013.D-6-2