[PS-12-5] Design of a Three-Terminal MTJ-Based Nonvolatile Logic Element with a 2-ns 64-Bit-Parallel Reconfiguration Capability

D. Suzuki¹, M. Natsui¹, A. Mochizuki¹, T. Hanyu¹ (1.Tohoku Univ. (Japan))

https://doi.org/10.7567/SSDM.2013.PS-12-5