Design Optimization Methodology for Ultra Low Power Analog Circuits using Intuitive Inversion-level and Saturation-level Parameter

T. Eimori; K. Anami; N. Yoshimatsu; T. Hasebe; K. Murakami

doi:https://doi.org/10.7567/SSDM.2013.PS-5-7

[PS-5-7] Design Optimization Methodology for Ultra Low Power Analog Circuits using Intuitive Inversion-level and Saturation-level Parameter

T. Eimori¹, K. Anami¹, N. Yoshimatsu¹, T. Hasebe², K. Murakami^1,3 (1.Institute of Systems, Information Technologies and Nanotechnologies, 2.Qualiarc Technology Solutions,Inc., 3.Kyushu Univ. (Japan))

https://doi.org/10.7567/SSDM.2013.PS-5-7

2013 International Conference on Solid State Devices and Materials

[PS-5-7] Design Optimization Methodology for Ultra Low Power Analog Circuits using Intuitive Inversion-level and Saturation-level Parameter