[A-8-3] A 500ps/8.5ns Array Read/Write Latency 1Mb Twin 1T1MTJ STT-MRAM designed in 90nm CMOS/40nm MTJ Process with Novel Positive Feedback S/A Circuit

T. Ohsawa¹, S. Miura², H. Honjo², S. Ikeda¹, T. Hanyu¹, H. Ohno¹, T. Endoh¹ (1.Tohoku Univ., 2.NEC Corp. (Japan))

https://doi.org/10.7567/SSDM.2014.A-8-3