[F-2-2] Quantitative Evaluation of Slow Traps near Ge MOS Interfaces by Using Time Response of MOS Capacitance

K. Tanaka^1,2、R. Zhang^1,2、M. Takenaka^1,2、S. Takagi^1,2 (1.Univ. of Tokyo、2.JST-CREST (Japan))

https://doi.org/10.7567/SSDM.2014.F-2-2