[F-2-5L] Sub-300^oC fabrication of poly-GeSn junctionless tri-gate p-FETs enabling sequential 3D integration of CMOS circuits

M. Kurosawa^1,2、Y. Kamata³、H. Ikenoue⁴、N. Taoka¹、O. Nakatsuka¹、T. Tezuka³、S. Zaima¹ (1.Nagoya Univ.、2.JSPS、3.AIST/GNC、4.Kyushu Univ. (Japan))

https://doi.org/10.7567/SSDM.2014.F-2-5L