Sub-300<sup>o</sup>C fabrication of poly-GeSn junctionless tri-gate p-FETs enabling sequential 3D integration of CMOS circuits

M. Kurosawa; Y. Kamata; H. Ikenoue; N. Taoka; O. Nakatsuka; T. Tezuka; S. Zaima

doi:https://doi.org/10.7567/SSDM.2014.F-2-5L

2014 International Conference on Solid State Devices and Materials

Sep 8, 2014 - Sep 11, 2014
Tsukuba International Congress Center (EPOCHAL TSUKUBA), Ibaraki, Japan

[F-2-5L] Sub-300^oC fabrication of poly-GeSn junctionless tri-gate p-FETs enabling sequential 3D integration of CMOS circuits

M. Kurosawa^1,2, Y. Kamata³, H. Ikenoue⁴, N. Taoka¹, O. Nakatsuka¹, T. Tezuka³, S. Zaima¹ (1.Nagoya Univ., 2.JSPS, 3.AIST/GNC, 4.Kyushu Univ. (Japan))

https://doi.org/10.7567/SSDM.2014.F-2-5L

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2014 International Conference on Solid State Devices and Materials

[F-2-5L] Sub-300oC fabrication of poly-GeSn junctionless tri-gate p-FETs enabling sequential 3D integration of CMOS circuits

[F-2-5L] Sub-300^oC fabrication of poly-GeSn junctionless tri-gate p-FETs enabling sequential 3D integration of CMOS circuits