The Japan Society of Applied Physics

[F-2-5L] Sub-300oC fabrication of poly-GeSn junctionless tri-gate p-FETs enabling sequential 3D integration of CMOS circuits

M. Kurosawa1,2、Y. Kamata3、H. Ikenoue4、N. Taoka1、O. Nakatsuka1、T. Tezuka3、S. Zaima1 (1.Nagoya Univ.、2.JSPS、3.AIST/GNC、4.Kyushu Univ. (Japan))

https://doi.org/10.7567/SSDM.2014.F-2-5L