[J-1-4] Fabrication Process and Thermal Stability of Isoelectronic Traps for High ON-current Si-based Tunnel Field-Effect Transistors

T. Mori¹, Y. Morita¹, N. Miyata¹, S. Migita¹, K. Fukuda¹, T. Yasuda¹, M. Masahara¹, H. Ota¹ (1.AIST (Japan))

https://doi.org/10.7567/SSDM.2014.J-1-4