High Reliability SRAM Development for 40nm Embedded Spilt Gate-MONOS

S. Okamoto; K. Maekawa; Y. Kawashima; K. Shiba; H. Sugiyama; M. Inoue; A. Nishida

doi:https://doi.org/10.7567/SSDM.2014.J-3-4

2014 International Conference on Solid State Devices and Materials

2014年9月8日〜 2014年9月11日
Tsukuba International Congress Center (EPOCHAL TSUKUBA), Ibaraki, Japan

[J-3-4] High Reliability SRAM Development for 40nm Embedded Spilt Gate-MONOS

S. Okamoto¹、K. Maekawa²、Y. Kawashima¹、K. Shiba²、H. Sugiyama¹、M. Inoue¹、A. Nishida¹ (1.Renesas Electronics Corp.、2.Renesas Semiconductor Manufacturing Co., Ltd. (Japan))

https://doi.org/10.7567/SSDM.2014.J-3-4

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