[J-3-5L] The Guideline of Si/SiGe Hetero-Junction Design in Parallel Plate Style TFETs (PP-TFETs) for Si CMOS Platform Implementation

M. Goto¹, Y. Kondo¹, Y. Morita², S. Migita², A. Hokazono¹, H. Ota², M. Masahara², S. Kawanaka¹ (1.Toshiba Corp., 2.GNC, AIST (Japan))

https://doi.org/10.7567/SSDM.2014.J-3-5L