Ultra Low-Frequency Noise in Vertical MOSFETs Having Tunable Threshold Voltage Fabricated with 60 nm CMOS Technology on 300 mm Wafer Process

T. Imamoto; T. Endoh

doi:https://doi.org/10.7567/SSDM.2014.J-7-1

2014 International Conference on Solid State Devices and Materials

2014年9月8日〜 2014年9月11日
Tsukuba International Congress Center (EPOCHAL TSUKUBA), Ibaraki, Japan

[J-7-1] Ultra Low-Frequency Noise in Vertical MOSFETs Having Tunable Threshold Voltage Fabricated with 60 nm CMOS Technology on 300 mm Wafer Process

T. Imamoto^1,2、T. Endoh^1,2,3 (1.Graduate School of Engineering, Tohoku Univ.、2.ACCEL, JST、3.Center for Innovative Integrated Electronic Systems, Tohoku Univ. (Japan))

https://doi.org/10.7567/SSDM.2014.J-7-1

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