[M-9-4L] Leakage-Delay Analysis of Monolithic 3D Logic Circuits using Ultra-Thin-Body InGaAs/Ge MOSFETs considering Interlayer Electrical Coupling

K.-C. Yu¹、M.-L. Fan¹、P. Su¹、C.-T. Chuang¹ (1.National Chiao Tung Univ. (Taiwan))

https://doi.org/10.7567/SSDM.2014.M-9-4L